The invention provides a method and a test system for an integrated circuit in which integrated voltage generators are changed over between different operating states for test purposes.
Integrated circuits, for example integrated memory chips, have internal or integrated voltage generators for different assemblies within the integrated circuit. An integrated voltage generator generates for example a voltage which is applied to a word line WL of a memory cell array within the integrated circuit.
FIG. 1A shows an arrangement according to the prior art, in which an internal voltage generator generates, in a manner dependent on an external supply voltage VDD and on a reference voltage generated by a reference voltage source, a voltage which switches by means of a switch S to a capacitive load, which is represented as a parallel value of a resistance RL in a capacitance CL. Conventional internal voltage generators can be changed over between an active operating mode and a standby operating mode. In the standby operating mode, the voltage generator requires a lower supply current IDD than in the active operating mode, such that the integrated circuit overall has a lower current consumption and the generation of heat is reduced.
The internal voltage generator is switched by means of an internal control signal CRTL, which is switched between an active and a standby operating state by an internal control unit of the integrated circuit, the internal control signal being applied to the internal voltage generator via a control signal path and, if appropriate, additional internal logic circuits. The internal switch S is also driven by the internal control signal CRTL.
If the switch S is opened, the load resistance RLOAD is very high or infinite and falls to a low load resistance upon closing at a switching instant tS, as is illustrated in FIG. 1B. At the same time, the internal voltage generator is changed over at the switching instant tS from the standby operating mode to an active operating mode in order to supply the necessary load voltage ULOAD. During the changeover process from the standby operating mode before the switching instant tS to the active operating state during a switching duration ΔtS, a voltage reduction of the load voltage ULOAD by a voltage value ΔU occurs, as is illustrated in FIG. 1C. The reduction of the load voltage ULOAD by the voltage ΔU during the switching process may lead, for example in the case of an integrated memory chip, to an unspecific malfunction in a memory cell array if the internal voltage generator supplies a switching voltage for a word line within the memory cell array.
One disadvantage of the switching arrangement according to the prior art as illustrated in FIG. 1A is that the switching instant tS for the switching of the switch S cannot be set independently of the control command for changing over the internal voltage generator between a standby operating state and an active operating state. In the case of a conventional circuit arrangement in accordance with FIG. 1A, therefore, the possibility of setting the voltage dip ΔU in the load voltage as illustrated in FIG. 1C for test purposes does not exist since the operating state of the internal voltage generator cannot be set independently of the switching state of the switch S.
Therefore, an object of the present invention is to provide a method and a test system in which the effect of a change in the load voltage generated by an integrated voltage generator on the functionality of the integrated circuit can be tested.